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| 74VHC16373 16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING s s s s s s s s s s HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = V NIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16373 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) TSSOP ORDER CODES PACKAGE TSSOP TUBE T &R 74VHC16373TTR PIN CONNECTION DESCRIPTION The 74VHC16373 is an advanced high-speed CMOS 16 BIT D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 16 bit D-TYPE latches are byte controlled by two latch enable inputs (nLE) and two output enable inputs(nOE). While the nLE input is held at a high level, the nQ outputs will follow the data (D) inputs. When the nLE is taken LOW, the nQ outputs will be latched at the logic level of D data inputs. When the (nOE) input is low, the nQ outputs will be in a normal logic state (high or low logic level); when nOE is at high level ,the outputs will be in a high impedance state. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. July 2001 1/10 74VHC16373 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 SYMBOL 1OE NAME AND FUNCTION IEC LOGIC SYMBOLS 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 24 2OE 3 State Output Enable Input (Active LOW) 25 2LE 36, 35, 33, 32, 2D0 to 2D7 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 41, 40, 38, 37 48 1LE 4, 10, 15, 21, GND 28, 34, 39, 45 7, 18, 31, 42 VCC Latch Enable Input Data Inputs Data Inputs Latch Enable Input Ground (0V) Positive Supply Voltage 3 State Output Enable Input (Active LOW) 1Q0 to 1Q7 3-State Outputs TRUTH TABLE INPUTS OE H L L L LE X L H H D X X L H OUTPUT Q Z NO CHANGE * L H X : Don`t Care Z : High Impedance * : Q outputs are latched at the time when the LE input is taken low logic level. 2/10 74VHC16373 LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V CC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 75 -65 to +150 300 Unit V V V mA mA mA mA C C ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol V CC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (note 1) (VCC = 3.3 0.3V) (V CC = 5.0 0.5V) Parameter Value 2 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 100 0 to 20 Unit V V V C ns/V 1) VIN from 30% to 70% of VCC 3/10 74VHC16373 DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low Level Output Voltage 2.0 3.0 4.5 3.0 4.5 I OZ High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current 5.5 0 to 5.5 5.5 IO=-50 A IO=-50 A IO=-50 A IO=-4 mA IO=-8 mA IO=50 A IO=50 A IO=50 A IO=4 mA IO=8 mA VI = VIH or VIL VO = VCC or GND VI = 5.5V or GND VI = VCC or GND TA = 25C Min. 1.5 0.7VCC Value -40 to 85C Min. 1.5 0.7VCC -55 to 125C Min. 1.5 0.7VCC Unit Typ. Max. Max. Max. V 0.5 0.3VCC VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage V IL 0.5 0.3VCC 0.5 0.3VCC V VOH 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 1.9 2.9 4.4 2.48 3.8 1.9 2.9 4.4 2.4 3.7 0.1 0.1 0.1 0.44 0.44 2.5 1 40 0.1 0.1 0.1 0.55 0.55 5 1 40 A A A V V 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.25 0.1 4 II ICC 4/10 74VHC16373 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 3.3 (*) 3.3 5.0 tPLH tPHL Propagation Delay Time Dn to Qn (*) (**) Value TA = 25C Min. Typ. 5.5 7 3.6 5 5.5 7.5 4 5 5.2 7.6 4 5 9 6 5 5 4 4 1 1 Max. 13 14.5 8.5 9.5 13 14 8.2 9.2 13 14.9 9.1 10.1 15.5 10.5 -40 to 85C Min. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 4 4 1 1 1.5 1 1.5 1 Max. 15 16.5 9.5 10.5 15 16 9.5 10.5 15 16 10 11.5 17 11.5 -55 to 125C Min. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 4 4 1 1 1.5 1 Max. 15 16.5 9.5 10.5 15 16 9.5 10.5 15 16 10 11.5 17 11.5 ns ns ns Unit CL (pF) 15 50 15 50 15 50 15 50 15 50 15 50 50 50 tPLH tPHL Propagation Delay Time LE to Qn 5.0(**) 3.3 3.3 5.0 tPZL tPZH Output Enable Time (*) (*) (**) 5.0(**) 3.3 (*) 3.3 (*) 5.0(**) 5.0 tPLZ tPHZ tw ts th tOSLH tOSHL Output Disable Time Pulse Width (LE) HIGH Setup Time Dn to LE HIGH or LOW (**) ns 3.3 (*) 5.0(**) 3.3 (*) 5.0 (**) ns ns 3.3 (*) 5.0 (**) ns Hold Time Dn to LE 3.3 (*) HIGH or LOW 5.0(**) Output to Output Skew time (note 1) 3.3 (*) 5.0 (**) ns 50 50 ns (*) Voltage range is 3.3V 0.3V (**) Voltage range is 5.0V 0.5V Note 1 : Parameter guaranteed by design. tsoLH = |t pLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) TA = 25C Min. Typ. 2.5 4 5.0 fIN = 10MHz 21 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF pF Unit CIN C OUT C PD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per Latch) 5/10 74VHC16373 DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol Parameter VCC (V) TA = 25C Min. Typ. 0.6 5.0 -0.9 C L = 50 pF 3.5 -0.6 Max. 0.9 V Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit VOLP V OLV V IHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 V 5.0 1.5 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ C L = 15/50 pF or equivalent (includes jig and probe capacitance) R L = R1 = 1K or equivalent R T = ZOUT of pulse generator (typically 50) SWITCH Open VCC GND 6/10 74VHC16373 WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 7/10 74VHC16373 WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 8/10 74VHC16373 TSSOP48 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.50 0.17 0.09 12.4 7.95 6.0 0.5 BSC 8 0.75 0 0.020 0.05 0.9 0.27 0.20 12.6 8.25 6.2 0.0067 0.0035 0.408 0.313 0.236 0.0197 BSC 8 0.030 TYP MAX. 1.1 0.15 0.002 0.035 0.011 0.0079 0.496 0.325 0.244 MIN. TYP. MAX. 0.043 0.006 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 7065588A 9/10 74VHC16373 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Swit zerland - United Kingdom (c) http://w ww.st.com 10/10 |
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